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LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver FEATURES

DESCRIPTIO
Fully Differential Input and Output Wide Supply Range: 2.375V to 12.6V Rail-to-Rail Output Swing Low Noise: 3nV/Hz Low Distortion, 2VP-P, 1MHz: -94dBc Adjustable Output Common Mode Voltage Unity Gain Stable Gain-Bandwidth: 70MHz Slew Rate: 65V/s Large Output Current: 85mA DC Voltage Offset <2mV MAX Open-Loop Gain: 100V/mV Low Power Shutdown 8-Pin MSOP or 3mm x 3mm DFN Package
The LT(R)1994 is a high precision, very low noise, low distortion, fully differential input/output amplifier optimized for 3V, single supply operation. The LT1994's output common mode voltage is independent of the input common mode voltage, and is adjustable by applying a voltage on the VOCM pin. A separate internal common mode feedback path provides accurate output phase balancing and reduced even-order harmonics. This makes the LT1994 ideal for level shifting ground referenced signals for driving differential input, single supply ADCs. The LT1994 output can swing rail-to-rail and is capable of sourcing and sinking up to 85mA. In addition to the low distortion characteristics, the LT1994 has a low input referred voltage noise of 3nV/Hz. This part maintains its performance for supply voltages as low as 2.375V. It draws only 13.3mA of supply current and has a hardware shutdown feature that reduces current consumption to 225A. The LT1994 is available in an 8-pin MSOP or 8-pin DFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Differential Input A/D Converter Driver Single-Ended to Differential Conversion Differential Amplification with Common Mode Translation Rail-to-Rail Differential Line Driver/Receiver Low Voltage, Low Noise, Differential Signal Processing
TYPICAL APPLICATIO
499 VIN 2VP-P 3V 0.1F 499
A/D Preamplifier: Single-Ended Input to Differential Output with Common Mode Level Shifting
3V 10F DIFFERENTIAL OUTPUT MAGNITUDE (dB)
0 FSAMPLE = 2.8Msps -10 F = 1.001MHz IN -20 INPUT = 2VP-P, SINGLE ENDED -30 SFDR = 93dB -40 -50 -60 -70 -80 -90 -100 -110 -120 0 1.05 0.35 0.70 FREQUENCY (MHz) 1.40
1994 TA01b
-+
VOCM LT1994 0.1F
24.9 47pF
AIN+ AIN-
VDD
SD0 CONV SCK 50.4MHz
+-
24.9
LTC1403A-1 GND VREF 10F
VOCM = 1.5V
499
499
1994 TA01
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LT1994 Driving an LTC1403A-1 1MHz Sine Wave, 8192 Point FFT Plot
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LT1994 ABSOLUTE
(Note 1)
AXI U RATI GS
Specified Temperature Range (Note 5) .... -40C to 85C Junction Temperature MS8 .................................................................. 150C DFN8................................................................. 125C Storage Temperature Range MS8 ................................................... -65C to 150C DFN8.................................................. -65C to 125C
Total Supply Voltage (V+ to V-) ..............................12.6V Input Voltage (Note 2)...............................................VS Input Current (Note 2)..........................................10mA Input Current (VOCM, SHDN) ................................10mA VOCM, SHDN .............................................................VS Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ... -40C to 85C
PACKAGE/ORDER I FOR ATIO
TOP VIEW IN- 1 VOCM 2 V+ 3 OUT+ 4 8 IN+ 7 SHDN 6V
-
5 OUT-
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN
TJMAX = 125C, JA = 160C/W UNDERSIDE METAL CONNECTED TO V-
ORDER PART NUMBER LT1994CDD LT1994IDD
DD PART MARKING* LBQM LBQM
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VOSDIFF PARAMETER Differential Offset Voltage (Input Referred)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+ = 3V, V- = 0V, VCM = VOCM = VICM = mid-supply, VSHDN = OPEN, RI = RF = 499, RL = 800 to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VICM is defined as (VIN+ + VIN-)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VIN+ - VIN-).
CONDITIONS VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = 5V VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = 5V VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = 5V MIN

VOSDIFF/T
Differential Offset Voltage Drift (Input Referred)
IB
Input Bias Current (Note 6)
2
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W
WW U
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TOP VIEW IN- 1 VOCM 2 V+ 3 OUT+ 4 8 7 6 5 IN+ SHDN V- OUT-
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 140C/W
ORDER PART NUMBER LT1994CMS8 LT1994IMS8
MS8 PART MARKING* LTBQN LTBQN
TYP
MAX 2 2 2 3

-45 -45 -45 -45
3 3 3 3 -18 -18 -18 -18
-3 -3 -3 -3
UNITS mV mV mV mV V/C V/C V/C V/C A A A A
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LT1994 ELECTRICAL CHARACTERISTICS
SYMBOL IOS PARAMETER Input Offset Current (Note 6)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+ = 3V, V- = 0V, VCM = VOCM = VICM = mid-supply, VSHDN = OPEN, RI = RF = 499, RL = 800 to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VICM is defined as (VIN+ + VIN-)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VIN+ - VIN-).
CONDITIONS VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = 5V Common Mode Differential Mode Differential MIN

RIN CIN en in enVOCM VICMR (Note 7) CMRRI (Note 8) CMRRIO (Note 8) PSRR (Note 9) PSRRCM (Note 9) GCM
Input Resistance Input Capacitance
TYP 0.2 0.2 0.2 0.2 700 4.5 2 3 2.5 15
MAX 2 2 3 4
UNITS A A A A k k pF nV/Hz pA/Hz nV/Hz
Differential Input Referred Noise Voltage f = 50kHz Density Input Noise Current Density f = 50kHz Input Referred Common Mode Output Noise Voltage Density Input Signal Common Mode Range Input Common Mode Rejection Ratio (Input Referred) VICM/VOSDIFF Output Common Mode Rejection Ratio (Input Referred) VOCM/VOSDIFF Differential Power Supply Rejection (VS/VOSDIFF) Output Common Mode Power Supply Rejection (VS/VOSOCM) Common Mode Gain (VOUTCM/VOCM) Common Mode Gain Error 100 * (GCM - 1) Output Balance (VOUTCM/VOUTDIFF) f = 50kHz, VOCM Shorted to Ground VS = 3V VS = 5V VS = 3V, VICM = 0.75V VS = 5V, VOCM = 2V VS = 3V to 5V VS = 3V to 5V VS = 2.5V VS = 2.5V VOUTDIFF = 2V Single-Ended Input Differential Input VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = 5V VS = 2.375V, VICM = VS/4 VS = 3V VS = 5V VS = 5V VS = 3V, 5V

0 -5 55 65 69 45
1.75 3.75 85 85 105 70 1 -0.15 1
V V dB dB dB dB V/V %
BAL

VOSCM
Common Mode Offset Voltage (VOUTCM - VOCM)
VOSCM/T
Common Mode Offset Voltage Drift
-65 -71 2.5 2.5 2.5 2.5 5 5 5 5 V- + 1.1 30 2.45 40 2.5 70 90 200 150 200 900
-46 -50 25 25 30 40
VOUTCMR (Note 7) RINVOCM VMID VOUT
Output Signal Common Mode Range (Voltage Range for the VOCM Pin) Input Resistance, VOCM Pin Voltage at the VOCM Pin Output Voltage, High, Either Output Pin (Note 10)

V+ - 0.8 60 2.55 140 175 400 325 450 2400
dB dB mV mV mV mV V/C V/C V/C V/C V k V mV mV mV mV mV mV
VS = 5V VS = 3V, No Load VS = 3V, RL = 800 VS = 3V, RL = 100 VS = 5V, No Load VS = 5V, RL = 800 VS = 5V, RL = 100

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LT1994 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Output Voltage, Low, Either Output Pin (Note 10)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+ = 3V, V- = 0V, VCM = VOCM = VICM = mid-supply, VSHDN = OPEN, RI = RF = 499, RL = 800 to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ - V-). VOUTCM is defined as (VOUT+ + VOUT-)/2. VICM is defined as (VIN+ + VIN-)/2. VOUTDIFF is defined as (VOUT+ - VOUT-). VINDIFF is defined as (VIN+ - VIN-).
CONDITIONS VS = 3V, No Load VS = 3V, RL = 800 VS = 3V, RL = 100 VS = 5V, No Load VS = 5V, RL = 800 VS = 5V, RL = 100 VS = 2.375V, RL = 10 VS = 3V, RL = 10 VS = 5V, RL = 10 VS = 5V, VCM = 0V, RL = 10 VS = 5V, VOUT+ = -VOUT- = 1V VS = 5V, VCM = 0V, VOUT+ = -VOUT- = 1.8V VS = 3V, TA = 25C VS = 5V, VCM = 0V, TA = 25C VS = 3V, RL = 800, fIN = 1MHz, VOUT+ - VOUT- = 2VP-P Differential Input 2nd Harmonic 3rd Harmonic Single-Ended Input 2nd Harmonic 3rd Harmonic VS = 3V, 0.01%, 2V Step VS = 3V, 0.1%, 2V Step VS = 3V VS = 3V VS = 5V VS = 5V VS = 3V VS = 5V VS = 5V VS = 3V to 5V VS = 3V to 5V VS = 2.375V to 5V VSHDN 0.5V to 3V VSHDN 3V to 0.5V MIN

ISC
Output Short-Circuit Current, Either Output Pin (Note 11)
SR
Slew Rate
25 30 40 45 50 50 58 58
TYP 30 50 125 80 125 900 35 40 65 85 65 65 70 70
MAX 70 90 250 180 250 2400
85 85
UNITS mV mV mV mV mV mV mA mA mA mA V/S V/S MHz MHz
GBW
Gain-Bandwidth Product (fTEST = 1MHz) Distortion
-99 -96 -94 -108 120 90 100

dBc dBc dBc dBc ns ns dB 12.6 V mA mA mA mA mA mA V V k s s 18.5 19.5 20.5 0.8 1.75 2.5 + - 2.1 V 75
tS AVOL VS IS
Settling Time Large-Signal Voltage Gain Supply Voltage Range Supply Current
2.375 13.3 13.9 14.8 0.225 0.375 0.7 V+ - 0.6 40 55 1 1
ISHDN
Supply Current in Shutdown
VIL VIH RSHDN tON tOFF
SHDN Input Logic Low SHDN Input Logic High SHDN Pull-Up Resistor Turn-On Time Turn-Off Time
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by a pair of back-to-back diodes. If the differential input voltage exceeds 1V, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely.
Note 4: The LT1994C/LT1994I are guaranteed functional over the operating temperature range -40C to 85C. Note 5: The LT1994C is guaranteed to meet specified performance from 0C to 70C. The LT1994C is designed, characterized, and expected to meet specified performance from -40C to 85C but is not tested or QA sampled at these temperatures. The LT1994I is guaranteed to meet specified performance from -40C to 85C. Note 6: Input bias current is defined as the average of the input currents flowing into Pin 1 and Pin 8 (IN- and IN+). Input Offset current is defined as the difference of the input currents flowing into Pin 8 and Pin 1 (IOS = IB+ - IB-).
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LT1994 ELECTRICAL CHARACTERISTICS
Note 7: Input Common Mode Range is tested using the Test Circuit of Figure 1 (RF = RI) by applying a single ended 2VP-P, 1kHz signal to VINP (VINM = 0), and measuring the output distortion (THD) at the common mode Voltage Range limits listed in the Electrical Characteristics table, and confirming the output THD is better than -40dB. The voltage range for the output common mode range (Pin 2) is tested using the Test Circuit of Figure 1 (RF = RI) by applying a 0.5V peak, 1kHz signal to the VOCM Pin 2 (with VINP = VINM = 0) and measuring the output distortion (THD) at VOUTCM with VOCM biased 0.5V from the VOCM pin range limits listed in the Electrical Characteristics Table, and confirming the THD is better than -40dB. Note 8: Input CMRR is defined as the ratio of the change in the input common mode voltage at the pins IN+ or IN- to the change in differential input referred voltage offset. Output CMRR is defined as the ratio of the change in the voltage at the VOCM pin to the change in differential input referred voltage offset. Note 9: Differential Power Supply Rejection (PSRR) is defined as the ratio of the change in supply voltage to the change in differential input referred voltage offset. Common Mode Power Supply Rejection (PSRRCM) is defined as the ratio of the change in supply voltage to the change in the common mode offset, VOUTCM - VOCM. Note 10: Output swings are measured as differences between the output and the respective power supply rail. Note 11: Extended operation with the output shorted may cause junction temperatures to exceed the 150C limit for the MSOP package (or 125C for the DD package) and is not recommended.
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Input Referred Voltage Offset vs Temperature
500 COMMON MODE VOLTAGE OFFSET (mV) VS = 3V VCM = 1.5V VOCM = 1.5V 250 FOUR TYPICAL UNITS 7.5
DIFFERENTIAL VOS (V)
5.0
INPUT BIAS CURRENT (A)
0
-250
-500
-750 -50
-25
0 25 50 TEMPERATURE (C)
Gain Bandwidth vs Temperature
72 71 GAIN BANDWIDTH (MHz) VS = 5V 70 GAIN (dB) VS = 3V 69 68 -1 67 66 -50 1 2
GAIN (dB)
-25
0 25 50 TEMPERATURE (C)
UW
75 75
Common Mode Voltage Offset vs Temperature
VS = 3V VCM = 1.5V VOCM = 1.5V FOUR TYPICAL UNITS -10
Input Bias Current and Input Offset Current vs Temperature
1.0 IB, VS = 5V -15 IOS, VS = 3V -20 IOS, VS = 5V 0 0.5
INPUT OFFSET CURRENT (A)
2.5
0
-25 IB, VS = 3V
-0.5
100
1994 G01
-2.5 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1994 G02
-30 -50
-25
0 25 50 TEMPERATURE (C)
75
-1.0 100
1994 G03
Frequency Response vs Supply Voltage
RF = RI = 499 VS = 3V VS = 2.5V VS = 5V 2
Frequency Response vs Load Capacitance
RF = RI = 499 VS = 2.5V 1
0 VS = 5V
0
VS = 3V
-1
100
1994 G04
-2
0.1
1 10 FREQUENCY (MHz)
100
1994 G05
-2
5pF FROM EACH OUTPUT TO GROUND 25pF FROM EACH OUTPUT TO GROUND 0.1 1 10 FREQUENCY (MHz) 100
1994 G06
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LT1994 TYPICAL PERFOR A CE CHARACTERISTICS
Output Impedance vs Frequency
100 VS = 3V RF = RI = 499 OUTPUT BALANCE (dB) -30 -40 DIFFERENTIAL PSRR (dB) ZOUT OUT+, OUT- () 10 -50 -60 -70 DIFFERENTIAL INPUT -80 0.1 0.1 1 10 FREQUENCY (MHz) 100
1994 G07
1
100 VS = 3V 90 INPUT CMRR (dB) 80 70 60 50 40 30 1k 10k 100k 1M FREQUENCY (Hz) VS = 5V
INPUT REFERRED VOLTAGE NOISE DENSITY (nV/Hz)
Input Common Mode Rejection vs Frequency
VICM VOSDIFF COMMON MODE PSRR (dB) 60
Differential Distortion vs Input Amplitude (Single Ended Input)
-60 VS = 3V FIN = 1MHz RF = RI = 499 -70 R = 800 L VOCM = MID-SUPPLY -80 2ND, VICM = 1.5V 2ND, VCM = V- 3RD, VCM = V- 3RD, VICM = 1.5V -110 1 2 3 VIN (VP-P) 4 5
1994 G13
DISTORTION HD2, HD3 (dB)
DISTORTION HD2, HD3 (dB)
-90
-100
6
UW
10M
1995 G10
Output Balance vs Frequency
VOUTCM VOUTDIFF 110 100 90 80 70 60 50 40 30 20 VS = 3V 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M
1995 G08
Differential Power Supply Rejection vs Frequency
VS VOSDIFF V+ SUPPLY V- SUPPLY
SINGLE ENDED INPUT
10 0
-90
VS = 3V 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M
1995 G09
Common Mode Output Power Supply Rejection vs Frequency
V- SUPPLY 50 40 V+ SUPPLY 30 20 10 VS = 3V 0 0.1 VS VOSOCM
Input Noise vs Frequency
100 VS = 3V TA = 25C 100 INPUT CURRENT NOISE DENSITY (pA/Hz)
10
10
en in 1 10 1 1M
1995 G12
100M
1 10 FREQUENCY (MHz)
100
1995 G11
100
1k 10k FREQUENCY (Hz)
100k
Differential Distortion vs Input Common Mode Level
-40 VS = 3V VIN = 2VP-P (SINGLE ENDED) -50 F = 1MHz IN RF = RI = 499 -60 RL = 800 VOCM = MID-SUPPLY -70 -80 -90 -100 3RD -110 0 2.5 0.5 1.5 2.0 1.0 INPUT COMMON MODE DC BIAS, IN- OR IN+ PINS (V)
1994 G14
2ND
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LT1994 TYPICAL PERFOR A CE CHARACTERISTICS
Differential Distortion vs Frequency
-40 68 VS = 3V V = 2VP-P (SINGLE ENDED) -50 F IN = 1MHz IN RF = RI = 499 -60 RL = 800 VOCM = MID-SUPPLY -70 VICM = MID-SUPPLY 3RD -80 -90 -100 -110 100k 60 -50 2ND
66 SLEW RATE (V/s) VS = 3V
VOUT = VOUT+ - VOUT- (0.5V/DIV)
DISTORTION (dB)
1M FREQUENCY (Hz)
Small Signal Step Response
25pF LOAD OUT+
0pF LOAD 20mV/DIV VS = 3V RF = RI = 499 VIN = 100mVP-P, SINGLE ENDED 0.5V/DIV
0.5V/DIV
OUT- VIN = 3VP-P SINGLE ENDED 20ns/DIV
1994 G18
UW
Slew Rate vs Temperature
RF = RI = 499
2V Step Response Settling
SETTLE VOLTAGE ERROR (2mV/DIV)
+0.1% ERROR VOUT
64 VS = 5V 62
-0.1% ERROR VS = 3V RF = RI = 499
10M
1994 G15
-25
0 25 50 TEMPERATURE (C)
75
100
1994 G16
25ns/DIV
1994 G17
Large Signal Step Response
VS = 3V RF = RI = 499 VCM = V-
Output with Large Input Overdrive
VS = 3V RF = RI = 499
OUT+
OUT+
OUT-
OUT-
VIN = 10VP-P SINGLE ENDED 2s/DIV
1994 G19 1994 G20
100ns/DIV
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LT1994 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
20 TOTAL SUPPLY CURRENT (mA) SHDN PIN VOLTAGE = V+ TOTAL SUPPLY CURRENT (mA) TA = 85C 16
15
12 TA = -40C 8 TA = 0C TA = 25C TA = 85C TA = 70C
TOTAL SUPPLY CURRENT (mA)
10
TA = 0C TA = 25C TA = 70C
5
0
0
2.5
5.0 7.5 10.0 SUPPLY VOLTAGE (V)
SHDN Pin Current vs SHDN Pin Voltage
0 VS = 3V TA = -40C -10 TA = 0C TA = 25C TA = 70C TA = 85C -20 SHUTDOWN SUPPLY CURRENT (A) 1000
SHDN PIN CURRENT (A)
-30
0
0.5
8
UW
TA = -40C
Supply Current vs SHDN Voltage
VS = 5V 16
Supply Current vs SHDN Voltage
VS = 3V
12 TA = -40C 8 TA = 85C
TA = 0C TA = 25C TA = 70C
4
4
12.5
1994 G21
0
0
1
2 3 4 SHDN PIN VOLTAGE (V)
5
1994 G22
0
0
0.5
1.5 2.0 2.5 1.0 SHDN PIN VOLTAGE (V)
3.0
1994 G23
Shutdown Supply Current vs Supply Voltage
750 TA = 25C 500 TA = 85C TA = -40C 250
0 1.5 2.0 2.5 1.0 SHDN PIN VOLTAGE (V) 3.0
1994 G24
0
2.5
7.5 10.0 5.0 SUPPLY VOLTAGE (V)
12.5
1994 G25
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LT1994 PI FU CTIO S
IN+, IN- (Pins 1, 8): Non-Inverting and Inverting Input Pins of the Amplifier, respectively. For best performance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit connections as short as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. VOCM (Pin 2): Output Common Mode Reference Voltage. The VOCM pin is the midpoint of an internal resistive voltage divider between the supplies, developing a (default) mid-supply voltage potential to maximize output signal swing. VOCM has a Thevenin equivalent resistance of approximately 40k and can be overdriven by an external voltage reference. The voltage on VOCM sets the output common mode voltage level (which is defined as the average of the voltages on the OUT+ and OUT- pins). VOCM should be bypassed with a high quality ceramic bypass capacitor of at least 0.1F (unless connected directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the IC. V+, V- (Pins 3, 6): Power Supply Pins. For single supply applications (Pin 6 grounded) it is recommended that high quality 1F and 0.1F ceramic bypass capacitors be placed from the positive supply pin (Pin 3) to the negative supply pin (Pin 6) with minimal routing. Pin 6 should be directly tied to a low impedance ground plane. For dual power supplies, it is recommended that high quality, 0.1F ceramic capacitors are used to bypass Pin 3 to ground and Pin 6 to ground. It is also highly recommended that high quality 1F and 0.1F ceramic bypass capacitors be placed across the power supply pins (Pins 3 and 6) with minimal routing. OUT+, OUT- (Pins 4, 5): Output Pins. Each pin can drive approximately 100 to ground with a short circuit current limit of up to 85mA. Each amplifier output is designed to drive a load capacitance of 25pF. This basically means the amplifier can drive 25pF from each output to ground or 12.5pF differentially. Larger capacitive loads should be decoupled with at least 25 resistors from each output. SHDN (Pin 7): When Pin 7 (SHDN) is floating or when Pin 7 is directly tied to V+, the LT1994 is in the normal operating mode. When Pin 7 is pulled a minimum of 2.1V below V+, the LT1994 enters into a low power shutdown state. Refer to the SHDN pin section under Applications Information for description of the LT1994 output impedance in the shutdown state.
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LT1994 APPLICATIO S I FOR ATIO
Functional Description The LT1994 is a small outline, wide band, low noise, and low distortion fully-differential amplifier with accurate output phase balancing. The LT1994 is optimized to drive low voltage, single-supply, differential input analog-to-digital converters (ADCs). The LT1994's output is capable of swinging rail-to-rail on supplies as low as 2.5V, which makes the amplifier ideal for converting ground referenced, single-ended signals into VOCM referenced differential signals in preparation for driving low voltage, single-supply, differential input ADCs. Unlike traditional op amps which have a single output, the LT1994 has two outputs to process signals differentially. This allows for two times the signal swing in low voltage systems when compared to single-ended output amplifiers. The balanced differential nature of the amplifier also provides even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). The LT1994 can be used as a single ended input to differential output amplifier, or as a differential input to differential output amplifier. The LT1994's output common mode voltage, defined as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the VOCM pin. If the pin is left open, there is an internal resistive voltage divider, which develops a potential halfway between the V+ and V- pins. The VOCM pin will have an equivalent Thevenin equivalent resistance of 40k, and a Thevenin equivalent voltage of half-supply. Whenever this pin is not hard tied to a low impedance ground plane, it is recommended that a high quality ceramic cap is used to bypass the VOCM pin to a low impedance ground plane (see Layout Considerations in this document). The LT1994's internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the VOCM pin. VOUT + + VOUT - VOUTCM = VOCM = 2 The outputs (OUT+ and OUT-) of the LT1994 are capable of swinging rail-to-rail. They can source or sink up to approximately 85mA of current. Each output is rated to
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drive approximately 25pF to ground (12.5pF differentially). Higher load capacitances should be decoupled with at least 25 of series resistance from each output. Input Pin Protection The LT1994's input stage is protected against differential input voltages that exceed 1V by two pairs of back-toback diodes that protect against emitter base breakdown of the input transistors. In addition, the input pins have steering diodes to either power supply. If the input pair is over-driven, the current should be limited to under 10mA to prevent damage to the IC. The LT1994 also has steering diodes to either power supply on the VOCM, and SHDN pins (Pins 2 and 7) and if exposed to voltages that exceed either supply, they too should be current limited to under 10mA. SHDN Pin If the SHDN pin (Pin 7) is pulled 2.1V below the positive supply, an internal current is generated that is used to power down the LT1994. The pin will have the Thevenin equivalent impedance of approximately 55k to V+. If the pin is left unconnected, an internal pull-up resistor of 120k will keep the part in normal active operation. Care should be taken to control leakage currents at this pin to under 1A to prevent leakage currents from inadvertently putting the LT1994 into shutdown. In shutdown, all biasing current sources are shut off, and the output pins OUT+ and OUT- will each appear as open collectors with a nonlinear capacitor in parallel, and steering diodes to either supply. Because of the non-linear capacitance, the outputs still have the ability to sink and source small amounts of transient current if exposed to significant voltage transients. The inputs (IN+, and IN-) have anti-parallel diodes that can conduct if voltage transients at the input exceed 1V. The inputs also have steering diodes to either supply. The turn-on and turn-off time between the shutdown and active states are on the order of 1s but depends on the circuit configuration. General Amplifier Applications As levels of integration have increased and, correspondingly, system supply voltages decreased, there has been
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LT1994 APPLICATIO S I FOR ATIO
a need for ADCs to process signals differentially in order to maintain good signal to noise ratios. These ADCs are typically supplied from a single supply voltage that can be as low as 2.5V and will have an optimal common mode input range near mid-supply. The LT1994 makes interfacing to these ADCs trivial, by providing both single ended to differential conversion as well as common mode level shifting. Figure 1 shows a general single supply application with perfectly matched feedback networks from OUT+ and OUT-. The gain to VOUTDIFF from VINM and VINP is: VOUTDIFF = VOUT + - VOUT - RF * (VINP - VINM ) RI
Note from the above equation that the differential output voltage (VOUT+ - VOUT-) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. This makes the LT1994 ideally suited pre-amplification, level shifting, and conversion of single ended signals to differential output signals in preparation for driving differential input ADCs. Effects of Resistor Pair Mismatch Figure 2 shows a circuit diagram that takes into consideration that real world resistors will not perfectly match. Assuming infinite open loop gain, the differential output relationship is given by the equation: VOUTDIFF = VOUT + - VOUT - * VICM - * VOCM, AVG AVG
RI VIN- RF V+ 0.1F VINM 3 1 VOCM VCM 0.1F VINP 2 8 4 0.1F VOUTCM RBAL VOUT+ RL
RF * VINDIFF + RI
-
VOCM
+ -
6
LT1994 5
+
7 VSHDN
0.1F V
-
RBAL VOUT-
1994 F01
RI VIN
+
RF
RL
Figure 1. Test Circuit
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where: RF is the average of RF1 and RF2, and RI is the average of RI1 and RI2. AVG is defined as the average feedback factor (or gain) from the outputs to their respective inputs: 1 RI2 RI1 + AVG = * 2 RI2 + RF2 RI1 + RF1 is defined as the difference in feedback factors: = RI2 RI1 - RI2 + RF2 RI1 + RF1 VICM is defined as the average of the two input voltages, VINP and VINM (also called the input common mode voltage): 1 VICM = * (VINP + VINM ) 2 and VINDIFF is defined as the difference of the input voltages: VINDIFF = VINP - VINM When the feedback ratios mismatch (), common mode to differential conversion occurs. Setting the differential input to zero (VINDIFF = 0), the degree of common mode to differential conversion is given
RI2 VIN- RF2 VOUT+ RL VS VINM 3 1 VOCM 0.1F VINP 2 8 4 0.1F
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-
VOCM
+ -
6
LT1994 5
+
SHDN 7
VSHDNB RI1 VIN
+
1994 F02
RF1
VOUT-
RL
Figure 2. Real-World Application
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LT1994 APPLICATIO S I FOR ATIO
by the equation: VOUTDIFF = VOUT + - VOUT - (VICM - VOCM ) * AVG VINDIFF = 0 In general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. Using 1% resistors or better will provide about 28dB of common mode rejection. Using 0.1% resistors will provide about 48dB of common mode rejection. A low impedance ground plane should be used as a reference for both the input signal source and the VOCM pin. A direct short of VOCM to this ground plane or bypassing the VOCM with a high quality 0.1F ceramic capacitor to this ground plane will further mitigate against common mode signals from being converted to differential. Input Impedance and Loading Effects The input impedance looking into the VINP or VINM input of Figure 1 depends on whether or not the sources VINP and VINM are fully differential. For balanced input sources (VINP = -VINM), the input impedance seen at either input is simply: RINP = RINM = RI For single ended inputs, because of the signal imbalance at the input, the input impedance actually increases over the balanced differential case. The input impedance looking into either input is: RINP = RINM = RI 1 RF 1- 2 * R + R I F VICM =
Input signal sources with non-zero output impedances can also cause feedback imbalance between the pair of feedback networks. For the best performance, it is recommended that the source's output impedance be compensated for. If input impedance matching is required by the source,
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R1 should be chosen (see Figure 3): R1 = RINM * RS RINM - RS According to Figure 3, the input impedance looking into the differential amp (RINM) reflects the single ended source case, thus: RINM = RI 1 RF 1- 2 * R + R I F R2 is chosen to balance R1 || RS: R2 = R1 * RS R1 + RS Input Common Mode Voltage Range The LT1994's input common mode voltage (VICM) is defined as the average of the two input voltages, VIN+, and VIN-. It extends from V- to approximately 1.25V below V+. The input common mode range depends on the circuit configuration (gain), VOCM and VCM (refer to Figure 4). For fully differential input applications, where VINP = -VINM, the common mode input is approximately: RI VIN+ + VIN- VOCM * + RI + RF 2 RF VCM * RF + RI
RINM RS VS R1 RI RF
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-
R1 CHOSEN SO THAT R1 || RINM = RS R2 CHOSEN TO BALANCE R1 || RS
+
LT1994
+
RI
-
RF
1994 F03
R2 = RS || R1
Figure 3. Optimal Compensation for Signal Source Impedance
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LT1994 APPLICATIO S I FOR ATIO
RI VIN- RF VOUT+ VS VINM 3 1 VOCM VCM 2 8 4 0.1F
RL
-
VOCM
+ -
6
LT1994 5
+
SHDN 7
VINP
VSHDNB RI VIN+ RF VOUT-
1994 F04
RL
Figure 4. Circuit for Common Mode Range
With singled ended inputs, there is an input signal component to the input common mode voltage. Applying only VINP (setting VINM to zero), the input common voltage is approximately: VICM RI VIN+ + VIN- = VOCM * + RI + RF 2
RF VINP RF VCM * * + RF + RI 2 RF + RI Output Common Mode Voltage Range The output common mode voltage is defined as the average of the two outputs: V + + VOUT - VOUTCM = VOCM = OUT 2 The VOCM sets this average by an internal common mode feedback loop which internally forces VOUT+ = -VOUT-. The output common mode range extends from approximately 1.1V above V- to approximately 0.8V below V+. The VOCM pin sits in the middle of an 80k to 80k voltage divider that sets the default mid-supply open circuit potential. In single supply applications, where the LT1994 is used to interface to an ADC, the optimal common mode input range to the ADC is often determined by the ADC's reference. If the ADC makes a reference available for setting
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the input common mode voltage, it can be directly tied to the VOCM pin, but must be capable of driving a 40k equivalent resistance that is tied to a mid-supply potential. If an external reference drives the VOCM pin, it should still be bypassed with a high quality 0.1F capacitor to a low impedance ground plane to filter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. Noise Considerations The LT1994's input referred voltage noise is on the order of 3nV/Hz. Its input referred current noise is on the order of 2.5pA/Hz. In addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. The output noise generated by both the amplifier and the feedback components is given by the equation: RF 2 e ni * 1+ R + 2 * (In * RF ) + I R 2 * e nRI * F + 2 * e nRF2 RI
2 2
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e no =
A plot of this equation and a plot of the noise generated by the feedback components are shown in Figure 6. The LT1994's input referred voltage noise contributes the equivalent noise of a 560 resistor. When the feedback
enRI22 RI2 RF2 enRF22
in-2
VS/2 3
encm
2
1 2 8
-
VOCM
+ -
6
4 eno2
LT1994 5
in+2
+
7
-VS/2 RF1 enRF12
enRI1
2
RI1
eni2
1994 F05
Figure 5. Noise Analysis
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LT1994 APPLICATIO S I FOR ATIO
network is comprised of resistors whose values are less than this, the LT1994's output noise is voltage noise dominant (See Figure 6): R e no e ni * 1 + F RI Feedback networks consisting of resistors with values greater than about 10k will result in output noise which is amplifier current noise dominant. e no 2 * In * RF Lower resistor values always result in lower noise at the penalty of increased distortion due to increased loading of the feedback network on the output. Higher resistor values will result in higher output noise, but improved distortion due to less loading on the output.
100 TOTAL (AMPLIFIER + FEEDBACK NETWORK) OUTPUT NOISE OUTPUT NOISE (nV/Hz)
10
FEEDBACK NETWORK NOISE ALONE
1 0.1
1 RF = RI (k)
10
1994 F06
Figure 6. LT1994 Output Spot Noise vs Spot Noise Contributed by Feedback Network Alone
Figure 6 shows the noise voltage that will appear differentially between the outputs. The common mode output noise voltage does not add to this differential noise. For optimum noise and distortion performance, use a differential output configuration.
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Power Dissipation Considerations The LT1994 is housed in either an 8-lead MSOP package (JA = 140C/W or an 8-lead DD package (JA = 160C/ W). The LT1994 combines high speed and large output current with a small die and small package so there is a need to be sure the die temperature does not exceed 150C if housed in the 8-lead MSOP package, and 125C if housed in the 8-lead DD package. In the 8-lead MSOP, LT1994 has its V- lead fused to the frame so it is possible to lower the package thermal impedance by connecting the V- pin to a large ground plane or metal trace. Metal trace and plated through holes can be used to spread the heat generated by the device to the backside of the PC board. For example, an 8-lead MSOP on a 3/32" FR-4 board with 540mm2 of 2oz. copper on both sides of the PC board tied to the V- pin can drop the JA from 140C/W to 110C/W (see Table 1). The underside of the DD package has exposed metal (4mm2) from the lead frame where the die is attached. This provides for the direct transfer of heat from the die junction to the printed circuit board to help control the maximum operating junction temperature. The dual-inline pin arrangement allows for extended metal beyond the ends of the package on the topside (component side) of a circuit board. Table 1 summarizes for both the MSOP and DD packages, the thermal resistance from the die junction to ambient that can be obtained using various amounts of topside, and backside metal (2oz. copper). On multilayer boards, further reductions can be obtained using additional metal on inner PCB layers connected through vias beneath the package. In general, the die temperature can be estimated from the ambient temperature TA, and the device power dissipation PD: TJ = TA+ + PD * JA
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LT1994 APPLICATIO S I FOR ATIO
The power dissipation in the IC is a function of the supply voltage, the output voltage, and the load resistance. For fully differential output amplifiers at a given supply voltage (VCC), and a given differential load (RLOAD), the worstcase power dissipation PD(MAX) occurs at the worst case quiescent current (IQ(MAX) = 20.5mA) and when the load current is given by the expression: ILOAD = VCC RLOAD
The worst case power dissipation in the LT1994 at V ILOAD = CC is: RLOAD PD(MAX) = 2 * VCC * ILOAD + IQ(MAX) - ILOAD2 * RLOAD V2 = CC + 2 * VCC * IQ(MAX) RLOAD
(
)
Example: A LT1994 is mounted on a circuit board in a MSOP-8 package (JA = 140C/W), and is running off of 5V supplies driving an equivalent load (external load plus feedback network) of 75. The worst-case power that would be dissipated in the device occurs when: VCC2 PD(MAX ) = + 2 * VCC * IQ(MAX ) = RLOAD 5V 2 + 2 * 5V * 17.5MA = 0.54W 75 The maximum ambient temperature the 8-lead MSOP is allowed to operate under these conditions is: TA = TJMAX - PD * JA = 150C - (0.54W) * (140C/W) = 75C
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To operate the device at higher ambient temperature, connect more copper to the V- pin to reduce the thermal resistance of the package as indicated in Table 1. Note that TJMAX for the 8-lead DD package is 125C (as opposed to 150C for the 8-lead MSOP), and the data for the equation above should be altered accordingly.
Table 1. LT1994 MSOP and DD Package Thermal Resistivity
LT1994 8-LEAD MSOP PACKAGE Copper Area Copper Area Thermal Topside Backside Resistance (mm2) (mm2) (Junction to Ambient) 0 30 100 100 540 0 0 0 100 540 140 135 130 120 110 LT1994 8-LEAD DD PACKAGE Copper Area Topside (mm2) 4 16 32 64 130 Thermal Resistance (Junction to Ambient) 160 135 110 95 70
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Layout Considerations Because the LT1994 is a high speed amplifier, it is sensitive to both stray capacitance and stray inductance. Components connected to the LT1994 should be connected with as short and direct connections as possible. A low noise, low impedance ground plane is critical for the highest performance. In single supply applications, high quality surface mount 1F and 0.1F ceramic bypass capacitors with minimum PCB trace should be used directly across the power supplies V+ to V-. In split supply applications, high quality surface mount 1F and 0.1F ceramic bypass capacitors should be placed across the power supplies V+ to V-, and individual high quality surface mount 0.1F bypass caps should be used from each supply to ground with direct (short) connections.
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LT1994 APPLICATIO S I FOR ATIO
Any stray parasitic capacitance to ground at the summing junctions, IN+ and IN- should be kept to an absolute minimum even if it means stripping back the ground plane away from any trace attached to this node. This becomes especially true when the feedback resistor network uses resistor values >500 in circuits with RF = RI. Excessive peaking in the frequency response can be mitigated by adding small amounts of feedback capacitance around RF (2pF to 5pF). Always keep in mind the differential nature of the LT1994, and that it is critical that the output impedances seen by both outputs (stray or intended) should be as balanced and symmetric as possible. This will help preserve the natural balance of the LT1994, which minimizes the generation of even order harmonics, and preserves the rejection of common mode signals and noise.
SI PLIFIED SCHE ATIC
V+ 120k SHUTDOWN CIRCUIT I1 CM1 V+ Q9 OUT- Q10 V- V- BIAS ADJUST + - Gm2B V+ I2 V+ Q1 IN- D1 D2 Q2 BIAS + - Gm2A BIAS ADJUST Q12 V- OUT+ +V R1 4k Q7 R2 4k OUT- V- V+ D3 D4 Q3 Q4 CM ADJUST I4A I4B Q5 Q6 V- V+ I3 Q8 80k V- V+ V+ 80k VOCM V- V+ I1 CM2 V+ Q11 OUT+ V- V+ 55k SHDN V+
V+
IN+
1994 SS01
V-
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It is highly recommended that the VOCM pin be either hard tied to a low impedance ground plane (in split supply applications) or bypassed to ground with a high quality 0.1F ceramic capacitor in single supply applications. This will help prevent thermal noise from the internal 80k-80k voltage divider (25nV/Hz) and other external sources of noise from being converted to differential noise due to mismatches in the feedback networks. It is also recommended that the resistive feedback networks be comprised of 1% resistors (or better) to enhance the output common mode rejection. This will also prevent VOCM input referred common mode noise of the common mode amplifier path (which cannot be filtered) from being converted to differential noise, degrading the differential noise performance.
V-
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LT1994 TYPICAL APPLICATIO S
Differential 1st Order Lowpass Filter Maximum -3dB frequency (f3dB) 5MHz Stopband attenuation: -6dB at 2 * f3dB and 14dB at 5 * f3dB
C11
VIN-
R11 V+
R21 0.1F 3 1 2
-+ +-
6 7
4
LT1994 5 VOUT-
0.1F
8
VIN+ R12 R22 VIN-
1994 TA03
C12
Component Calculation: R11 = R12, R21 = R22 f3dB 5MHz and Gain 5MHz f3dB
1. Calculate an absolute value for C11 (C11abs) using a specified -3dB frequency 4 * 105 C11abs = (C11abs in pF and f3dB in kHz) f3dB 2. Select a standard 5% capacitor value nearest the absolute value for C11 3. Calculate R11 and R21 using the standard 5% C11 value, f3dB and desired gain R11 and R21 equations (C11 in pF and f3dB in kHz) R21= R11= 159.2 * 106 C11* f3dB R21 Gain
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Example: The specified -3dB frequency is 1MHz Gain = 4 1. Using f3dB = 1000kHz, C11abs = 400pF 2. Nearest standard 5% value to 400pF is 390pF and C11 = C12 = 390pF 3. Using f3dB = 1000kHz, C11 = 390pF and Gain = 4, R21 = R22 = 412 and R11 = R12 = 102 (nearest 1% value) Differential 2nd Order Butterworth Lowpass Filter
VOUT
+
Maximum -3dB frequency (f3dB) 2.5MHz Stopband attenuation: -12dB at 2 * f3dB and -28dB at 5 * f3dB
R21 R11 R31 V+ 0.1F 3 1 C11 0.1F 2 8 4 C21
-+ +-
6 7
VOUT+ VOUT-
LT1994 5
VIN+ R12 R32 C22
1994 TA04
R22
Component Calculation: R11 = R12, R21 = R22, R31 = R32, C21 = C22, C11 = 10 * C21, R1 = R11, R2 = R21, R3 = R31, C2 = C21 and C1 = C11
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LT1994 TYPICAL APPLICATIO S
1. Calculate an absolute value for C2 (C2abs) using a specified -3dB frequency C2abs = 4 * 105 (C2abs in pF and f3dB in kHz) (Note 2) f3dB Example: The specified -3dB frequency is 1MHz Gain = 1 1. Using f3dB = 1000kHz, C2abs = 400pF 2. Nearest standard 5% value to 400pF is 390pF and C21 = C22 = 390pF and C11 = 3900pF 3. Using f3dB = 1000kHz, C2 = 390pF and Gain = 1, R1 = 549, R2 = 549 and R3 = 15.4 (nearest 1% values). R11 = R21 = 549, R21 = R22 = 549 and R31 = R32 = 15.4. Note 1: The equations for R1, R2, R3 are ideal and do not account for the finite gain bandwidth product (GBW) of the LT1994 (70MHz). The maximum gain is set by the C1/C2 ratio (which for convenience is set equal to ten). Note 2: The calculated value of a capacitor is chosen to produce input resistors less than 600. If a higher value input resistance is required then multiply all resistor values and divide all capacitor values by the same number.
2. Select a standard 5% capacitor value nearest the absolute value for C2 (C1 = 10 * C2) 3. Calculate R3, R2 and R1 using the standard 5% C2 value, the specified f3dB and the specified passband gain (Gn) f3dB 2.5MHz and Gain 8.8 or Gain 2.5MHz f3dB
R1, R2 and R3 equations (C2 in pF and f3dB in kHz)
(1.121- R3 =
R2 = R1= R2 Gn
(1.131- 0.127 * Gn) ) * 108 (Note 1) (Gn + 1) * C2 * f3dB
1.266 * 1015 R3 * C22 * f3dB2
A Single Ended to Differential Voltage Conversion with Source Impedance Matching and Level Shifting
RS = 50 VIN 50 374 V+ 54.9 3 1 V VIN t 402 0.1F 2 8 0.1F 4 V 402
1 0 -1
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-+ +-
6 7
VOUT- VOUT+
VOCM LT1994 5
VOCM + 0.25V VOCM VOCM - 0.25V 0
VOUT+ VOUT- t
1994 TA05
402
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LT1994 PACKAGE DESCRIPTIO U
DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 5 0.675 0.05 0.38 0.10 8 3.00 0.10 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (NOTE 6)
(DD8) DFN 1203
3.5 0.05 1.65 0.05 2.15 0.05 (2 SIDES)
1.65 0.10 (2 SIDES)
0.200 REF
0.75 0.05
4 0.25 0.05 2.38 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.00 0.102 (.118 .004) (NOTE 3) 0.52 (.0205) REF
8
7 65
5.23 (.206) MIN
3.20 - 3.45 (.126 - .136)
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
GAUGE PLANE
0.42 0.038 (.0165 .0015) TYP
0.65 (.0256) BSC
DETAIL "A" 0.18 (.007)
1
23
4
0.53 0.152 (.021 .006)
RECOMMENDED SOLDER PAD LAYOUT
1.10 (.043) MAX
0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING PLANE
0.22 - 0.38 (.009 - .015) TYP
0.65 (.0256) BSC
0.127 0.076 (.005 .003)
MSOP (MS8) 0204
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1994 TYPICAL APPLICATIO U
RFID Receiver Front-End, 20kHz < -3dB BW < 5MHz (Baseband Gain = 2)
0.056F 82pF 140 5V 0.1F 1 5V BPF RF+ VCC LT5516 IOUT 0
+
402
3 4 LT1994 5 6 402 82pF IOUT
7 5V 270pF 0.1F 0.056F 140 2 8
RF-
IOUT- 270pF 5V
82pF 0.056F
LO INPUT
270pF LO+ 0/90 LO- 90 QOUT- 270pF 1 7 5V 0.1F 0.056F 140 2 8 6 402 82pF
1994 TA02
QOUT
+
140 5V
402 0.1F 3 4 LT1994 5 QOUT
ENABLE
EN
RELATED PARTS
PART NUMBER LT1167 LT1806/LT1807 LT1809/LT1810 LT1990 LT1991 LTC1992/LTC1992-x LT1993-2/-4/-10 LT1995 LT1996 LT6600-2.5/-5/-10/-15/-20 DESCRIPTION Precision, Instrumentation Amp Single/Dual Low Distortion Rail-to-Rail Amp Single/Dual Low Distortion Rail-to-Rail Amp High Voltage Gain Selectable Differential Amp Precision Gain Selectable Differential Amp Fully Differential Input/Output Amplifiers Low Distortion and Noise, Differential In/Out High Speed Gain Selectable Differential Amp Precision, 100A, Gain Selectable Differential Amp Differential Amp and Lowpass, Chebyshev Filter COMMENTS Single Gain Set Resistor: G = 1 to 10,000 325MHz, 140V/s Slew Rate, 3.5nV/Hz Noise 180MHz, 350V/s Slew Rate, Shutdown 250V Common Mode, Micropower, Gain = 1, 10 Micropower, Pin Selectable Gain = -13 to 14 Programmable Gain or Fixed Gain (G = 1, 2, 5, 10) Fixed Gain (G = 2, 4, 10) 30MHz, 1000V/s, Pin Selectable Gain = -7 to 8 Pin Selectable Gain = 9 to 117 Filter Cutoff = 2.5MHz, 5MHz, 10MHz, 15MHz or 20MHz
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20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0306 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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